Microelectronic devices generally have a semiconductor die (i.e., a chip) that includes integrated circuitry with a high density of very small components. Typically, dies include an array of very small bond pads electrically coupled to the integrated circuitry. The bond pads are external electrical contacts through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. After dies are formed, dies are “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines. Conventional processes for packaging dies include electrically coupling the bond pads on the dies to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the dies to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact).
Different types of semiconductor dies may have widely different bond pad arrangements, and yet should be compatible with similar external devices. Accordingly, existing packaging techniques can include attaching a redistribution layer (RDL) to a semiconductor die. The RDL includes lines and/or vias that connect the die bond pads with RDL bond pads. An array of leads, ball-pads, or other types of electrical terminals of the RDL bond pads are arranged to mate with the bond pads of external devices. In one typical “Chip First” packaging process, a die is mounted on a carrier and encapsulated. The carrier is then removed and an RDL is subsequently formed directly on a front side of the die where the die bond pads are located using deposition and lithography techniques. In another typical “Chip Last” packaging process, an RDL is formed apart from a die and then the die is subsequently mounted to the RDL and encapsulated. However, one drawback of both Chip First and Chip Last packaging processes is that the resulting package is subject to warpage.